Calibration Sub-Stage (CAL_SUB_STAGE) - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

Each calibration stage has its own set of sub-stages. CAL_SUB_STAGE provides the information of the sub stage being run during a calibration stage. This location is valid only when the current calibration stage status is in-progress.

Table 1. Calibration Sub-Stage Status
Calibration Stage Sub-Stage Description
DQS Gate Calibration 0 Initializing internal variables
1 Finding third edge stage. Rank-wise.
2 Stable 0 confirmation before the third rise edge. Rank-wise.
3 Find left edge of the noise of the third edge using fine taps of step size bigger than 1. Ranks wise.
4 Find noise width of the third edge using fine taps of step size 1. Rank wise.
5 Align to the center of noise using fine taps. Rank-wise.
6 Add extra read latency of 1 to allow gate logic to capture full burst of the dqs. Rank-wise.
7 Multi-rank read latency and coarse adjustments.
8 DQS gate calibration exiting
Write Leveling 0 Finding the 0x1 edge detection. Rank-wise sequential.
1 Stage 0 confirmation. Rank-wise sequential.
2 Align to the center of noise using fine taps. Rank-wise sequential.
Write Latency 0 Finding required latency and adjustment. Rank-wise.
1 Multi rank write latency and coarse adjustment
2 Sanity Check. Rank-wise.
Write DQ Per-bit Deskew and Centering 0 Initializing internal variables
1 DDR initialization sequence
2 Finding best DQS delay offset
3 Finding valid to noise region
4 Finding left edge of noise
5 Centering phase
Read DQ Per-bit Deskew and Centering 0 Initializing internal variables
1 Move PDQS and NDQS to valid region of their associated data bits
2 Move all the DQ lines to valid region sampling of their associated PDQS
3 Move all the DQ lines to get start of the noise region sampling of their associated PDQS
4 Move all the DQS lines together to get the noise region sampling of their associated NDQS
5 Move PDQS and NDQS using fine taps of step size of 1 to get noise to valid region crossing
6 Move PDQS and NDQS using fine taps of step size of more than 1 to get valid to noise region crossing
7 Move PDQS and NDQS backward by one step size to go back to last valid sampling region
8 Move PDQS and NDQS using fine taps of step size of 1 to get valid to noise region crossing
9 Move PDQS and NDQS to center of the detected valid window
10 Check sanity of the read data calibration
11 Read calibration exiting