The memory interface requires one XPLL per I/O bank used by the memory interface and BUFGs. These clocking components are used to create the proper clock frequencies and phase shifts necessary for the proper operation of the memory interface.
There are two XPLLs per bank. If a bank is shared by two memory interfaces, both XPLLs in that bank are used.
Note:
DDR4 SDRAM generates the appropriate
clocking structure and no modifications to the RTL are supported.
The DDR4 SDRAM IP generates the appropriate clocking structure for the desired interface. This structure must not be modified. The allowed clock configuration is as follows:
- Differential reference clock source connected to GCIO
- GCIO to XPLL (located in center bank of memory interface)
- XPLL to BUFG (located at center bank of memory interface) driving the AMD Versal™ adaptive SoC logic and all XPLLs
- XPLL to BUFG (located at center bank of memory interface) divide by two mode driving 1/2 rate Versal adaptive SoC logic