When the user logic app_en signal is asserted and the
app_rdy signal is asserted from the user interface, a command is
accepted and written to the FIFO by the user interface. The command is ignored by the
user interface whenever app_rdy is deasserted. The user logic needs to
hold app_en High along with the valid command, autoprecharge, and
address values until app_rdy is asserted as shown for the "write with
autoprecharge" transaction in the following figure.
A non back-to-back write command can be issued as shown in the following
figure. This figure depicts three scenarios for the app_wdf_data,
app_wdf_wren, and app_wdf_end signals as
follows:
- Write data is presented along with the corresponding write command.
- Write data is presented before the corresponding write command.
- Write data is presented after the corresponding write command, but should not exceed the limitation of two clock cycles.
For write data that is output after the write command has been registered, as shown in #3, the maximum delay is two clock cycles.
