Required Constraints
For DDR4 SDRAM Vivado IDE, you specify the pin location constraints. For more information on I/O standard and other constraints, see the Vivado Design Suite User Guide: I/O and Clock Planning (UG899). The location is chosen by the Vivado IDE according to the banks and byte lanes chosen for the design.
The I/O standard is chosen by the memory type selection and options in the
Vivado IDE and by the pin type. A sample for
dq[0]
is shown here.
set_property PACKAGE_PIN AF20 [get_ports "c0_ddr4_dq[0]"]
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[0]"]
The system clock must have the period set properly:
create_clock -name c0_sys_clk -period 10 [get_ports c0_sys_clk_p]
Device, Package, and Speed Grade Selections
This section is not applicable for this IP core.
Clock Frequencies
This section is not applicable for this IP core.
Clock Management
For more information on clocking, see the related information.
Clock Placement
This section is not applicable for this IP core.
Banking
This section is not applicable for this IP core.
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
The DDR4 SDRAM tool generates the appropriate I/O standards and placement based on the selections made in the Vivado IDE for the interface type and options.
set_input_delay
and set_output_delay
constraints are not needed on the external memory interface pins in this design due
to the calibration process that automatically runs at start-up. Warnings seen during
implementation for the pins can be ignored.