Core Overview - 1.0 English

The DDR4 SDRAM core provides solutions for interfacing with the SDRAM memory type. Both a complete Memory Controller and a physical (PHY) layer only solution are supported. The Versal adaptive SoC for the DDR4 SDRAM core are organized in the following high-level blocks:

Controller

The controller accepts burst transactions from the user interface and generates transactions to and from the SDRAM. The controller takes care of the SDRAM timing parameters and refresh. It coalesces write and read transactions to reduce the number of dead cycles involved in turning the bus around. The controller also reorders commands to improve the utilization of the data bus to the SDRAM.

Physical Layer

The physical layer provides a high-speed interface to the SDRAM. This layer includes the hard blocks inside the Versal adaptive SoC and the soft blocks calibration logic necessary to ensure optimal timing of the hard blocks interfacing to the SDRAM.

The application logic is responsible for all SDRAM transactions, timing, and refresh. These hard blocks include:

• Data serialization and transmission
• Data capture and deserialization
• High-speed clock generation and synchronization
• Coarse and fine delay elements per pin with voltage and temperature tracking

The soft blocks include:

Memory Initialization

The calibration modules provide a JEDEC®-compliant initialization routine for the particular memory type. The delays in the initialization process can be bypassed to speed up simulation time, if desired.

Calibration

The calibration modules provide a complete method to set all delays in the hard blocks and soft IP to work with the memory interface. Each bit is individually trained and then combined to ensure optimal interface performance.

Results of the calibration process are available through the AMD debug tools. After completion of calibration, the PHY layer presents raw interface to the SDRAM.

Application Interface

The user interface layer provides a simple FIFO-like interface to the application. Data is buffered and read data is presented in request order.

The above user interface is layered on top of the native interface to the controller. The native interface is not accessible by the user application and has no buffering and presents return data to the user interface as it is received from the SDRAM which is not necessarily in the original request order. The user interface then buffers the read and write data and reorders the data as needed.