Customizing and Generating the Core - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)
Document ID
PG353
Release Date
2023-10-18
Version
1.0 English
CAUTION:
Microsoft Windows operating system has a 260-character limit for path lengths, which can affect the AMD Vivado™ Integrated Design Environment (IDE). To avoid this issue, use the shortest possible names and directory locations when creating projects, defining IP or managed IP projects, and creating block designs.
CAUTION:
For AMD Versal™ Soft DDR4 IP standalone/Vivado IP integrator designs with no debug cores (ILA/VIO), the Vivado IDE requires the CIPS IP with PL clock and PL reset ports enabled to be present in the design. Access the CIPS IP in the Vivado IP catalog and instantiate the CIPS IP using the default configuration with PL clock and PL reset port enabled.

This section includes information about using AMD tools to customize and generate the core in the AMD Vivado™ Design Suite.

If you are customizing and generating the core in the Vivado IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl console.

You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:

  1. Select the IP from the IP catalog.
  2. Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).

Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might vary from the current version.