SDRAM | app_addr Mapping |
---|---|
Rank | (RANK == 1) ? 1’b0: (S_HEIGHT == 1) ? app_addr[COL_WIDTH + ROW_WIDTH+ BANK_WIDTH + BANK_GROUP_WIDTH +: RANK_WIDTH]: app_addr[COL_WIDTH + ROW_WIDTH + BANK_WIDTH + BANK_GROUP_WIDTH + LR_WIDTH +: RANK_WIDTH] |
Logical Rank (3DS) | (S_HEIGHT == 1) ? 1’b0: app_addr[COL_WIDTH + ROW_WIDTH + BANK_WIDTH + BANK_GROUP_WIDTH +: LR_WIDTH] |
Row | app_addr[COL_WIDTH +: ROW_WIDTH] |
Column | app_addr[0 +: COL_WIDTH] |
Group | app_addr[COL_WIDTH + ROW_WIDTH + BANK_WIDTH +: BANK_GROUP_WIDTH] |
Bank | app_addr[COL_WIDTH + ROW_WIDTH +: BANK_WIDTH] |