DDR4 Basic Tab - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

The following figure shows the DDR4 Basic tab.

Figure 1. DDR4 Basic Tab
Important: All parameters shown in the controller options dialog box are limited selection options in this release.

For the Vivado IDE, all controllers can be created and available for instantiation.

In IP integrator, only one controller instance of AMD Versal™ Soft DDR4 Memory Controller can be created for instantiation:

  1. After a controller is added in the pull-down menu, select the Mode and Interface for the controller. Select the AXI4 Interface or have the option to select the Generate the PHY component only.
  2. Select the settings in the Clocking.

    In Clocking, the Memory Time period sets the speed of the interface. The speed entered drives the available Input Clock Time period. For more information on the clocking structure, see the Clocking section.