The following table shows the DDR4 debug signals.
| Signal | Signal Width | Signal Description |
|---|---|---|
| init_calib_complete | [0:0] | Signifies the status of
calibration. 1’b0 = Calibration not complete. 1’b1 = Calibration completed successfully. |
| cal_r*_status | [127:0] | Signifies the status of each stage of calibration. See
Table 1 for decoding information. See the
following relevant debug sections for usage information. Note: The * indicates the rank value. Each
rank has a separate cal_r*_status bus.
|
| cal_post_status | [8:0] | Signifies the status of the memory core after calibration has finished. See Table 1 for decoding information. |
| dbg_cal_seq | [2:0] | Calibration sequence indicator,
when RTL is issuing commands to the DRAM. [0] = 1’b0 -> Single Command Mode, one DRAM command only. 1’b1 -> Back-to-Back Command Mode. RTL is issuing back-to-back commands. [1] = Write Leveling Mode [2] = Extended write mode enabled, where extra data and DQS pulses are sent to the DRAM before and after the regular write burst. |
| dbg_cal_seq_cnt | [31:0] | Calibration command sequence count used when RTL is issuing commands to the DRAM. Indicates how many DRAM commands are requested (counts down to 0 when all commands are sent out). |
| dbg_cal_seq_rd_cnt | [7:0] | Calibration read data burst count (counts down to 0 when all expected bursts return), used when RTL is issuing read commands to the DRAM. |
| dbg_rd_valid | [0:0] | Read Data Valid |
| dbg_cmp_byte | [5:0] | Calibration byte selection (used to determine which byte is currently selected and displayed in dbg_rd_data). |
| dbg_rd_data | [63:0] | Read Data from Input FIFOs. |
| dbg_rd_data_cmp | [63:0] | Comparison of dbg_rd_data and dbg_expected_data. |
| dbg_expected_data | [63:0] | Displays the expected data during calibration stages that use general interconnect-based data pattern comparison such as Read per-bit deskew or read DQS centering (complex). |
| dbg_cplx_config | [15:0] | Complex Calibration
Configuration [0] = Start [1] = 1’b0 selects the read pattern. 1’b1 selects the write pattern. [3:2] = Rank selection [8:4] = Byte selection [15:9] = Number of loops through data pattern. |
| dbg_cplx_status | [1:0] | Complex Calibration Status [0] = Busy [1] = Done |
| dbg_io_address | [27:0] | MicroBlaze I/O Address Bus |
| dbg_pllGate | [0:0] | PLL Lock Indicator |