DDR4 LRDIMM Calibration Sequence - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

The following data buffer calibration stages are added to meet the timing between the data buffer and DRAMs and these are repeated for each and every rank of the LRDIMM card/slot.

  • MREP Training
  • MRD Cycle Training
  • MRD Center Training
  • DWL Training
  • MWD Cycle Training
  • MWD Center Training

Whereas the host side calibration stages would exercise the timing between host and data buffer and they are performed once per every LRDIMM card/slot.

All the calibration stages between data buffer and DRAMs are exercised first and then the host side calibration stages are exercised.

During the calibration stages between Data buffer and DRAM, the status value is placed on the DQ pins. At the time of these calibration stages, XPHY RX Gating is disabled and the Reference clock is used to sample the DQ values.

At the end of each of the data buffer calibration stages, Per Buffer Addressing (PBA) mode is enabled to program the calibrated latency and the delay values into the data buffer registers.

The following sections describe the data buffer calibration stages.