DDR4 Post-Calibration Status - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

The following table shows the DDR4 cal_post_status signal.

Table 1. DDR4 Post-Calibration Status
Debug Signal Bit Description Post-Calibration Step
cal_post_status 0 Running DQS Gate Tracking
1 Idle
2 Fail
3 Running Read Margin Check (Reserved)
4 Running Write Margin Check (Reserved)
5   Handshake Failure (Reserved)
6   Margin Check Failure (Reserved)
7   Reserved
8   Reserved