DDR4 “ROW_BANK_COLUMN” Mapping - 1.0 English

The “ROW_COLUMN_BANK” setting maps app_addr[4:3] to the DDR4 bank group bits used by the controller to interleave between its group FSMs. The lower order address bits equal to app_addr[5] and above map to the remaining SDRAM bank and column address bits. The highest order address bits map to the SDRAM row. This mapping is ideal for workloads that have address streams that increment linearly by a constant step size of hex 8 for long periods. With this configuration and workload, transactions sent to the user interface are evenly interleaved across the controller group FSMs, making the best use of the controller resources.

In addition, this arrangement tends to generate hits to open pages in the SDRAM. The combination of group FSM interleaving and SDRAM page hits results in very high SDRAM data bus usage.

Address streams other than the simple increment pattern tend to have lower SDRAM bus usage. You can recover this performance loss by tuning the mapping of your design flat address space to the app_addr input port of the user interface. If you have knowledge of your address sequence, you can add logic to map your address bits with the highest toggle rate to the lowest app_addr bits, starting with app_addr[3] and working up from there.

For example, if you know that your workload address Bits[4:3] toggle much less than Bits[10:9], which toggle at the highest rate, you could add logic to swap these bits so that your address Bits[10:9] map to app_addr[4:3]. The result is an improvement in how the address stream interleaves across the controller group FSMs, resulting in better controller throughput and higher SDRAM data bus usage.