DDR4 “ROW_COLUMN_BANK” Mapping - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)
Document ID
PG353
Release Date
2023-10-18
Version
1.0 English
Table 1. DDR4 “ROW_COLUMN_BANK” Mapping
SDRAM app_addr Mapping
Rank (RANKS == 1) ? 1'b0:

(S_HEIGHT == 1) ? app_addr[COL_WIDTH + ROW_WIDTH + BANK_WIDTH + BANK_GROUP_WIDTH +: RANK_WIDTH]:

app_addr[COL_WIDTH + ROW_WIDTH + BANK_WIDTH + BANK_GROUP_WIDTH + LR_WIDTH +: RANK_WIDTH]
Logical Rank (3DS) (S_HEIGHT==1) ? 1'b0:

app_addr[BANK_GROUP_WIDTH + BANK_WIDTH + COL_WIDTH + ROW_WIDTH +: LR_WIDTH]
Row app_addr[BANK_GROUP_WIDTH + BANK_WIDTH + COL_WIDTH +: ROW_WIDTH
Column app_addr[3 + BANK_GROUP_WIDTH + BANK_WIDTH +: COL_WIDTH - 3], app_addr[2:0]
Bank app_addr[3 + BANK_GROUP_WIDTH +: BANK_WIDTH
Bank Group app_addr[3 +: BANK_GROUP_WIDTH]