DDR4 ROW_COLUMN_LRANK_BANK - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)
Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

The following table shows the “ROW_COLUMN_LRANK_BANK” mappings for DDR4 with 3DS examples.

Table 1. DDR4 ROW_COLUMN_LRANK_BANK
SDRAM app_addr Mapping
Rank (RANK == 1) ? 1’b0:

app_addr[ROW_WIDTH + COL_WIDTH + LR_WIDTH + BANK_WIDTH + BANK_GROUP_WIDTH +: RANK_WIDTH]
Logical_rank app_addr[3 + BANK_WIDTH + BANK_GROUP_WIDTH +: LR_WIDTH]
Row app_addr[COL_WIDTH + LR_WIDTH + BANK_WIDTH + BANK_GROUP_WIDTH +: ROW_WIDTH]
Column app_addr[3 + LR_WIDTH + BANK_WIDTH + BANK_GROUP_WIDTH +: COL_WIDTH - 3], app_addr[2:0]
Bank app_addr[3 + BANK_GROUP_WIDTH +: BANK_WIDTH]
Group app_addr[3 +: BANK_GROUP_WIDTH]