The following table shows the DDR4 cal_r*_status
signal.
Debug Signal | Bit | Description | Calibration Step |
---|---|---|---|
cal_r*_status | 0 | Start | PHY_BISC |
1 | Done | ||
2 | Start | MEM_INIT | |
3 | Done | ||
4 | Start | Reserved | |
5 | Done | ||
6 | Start | Reserved | |
7 | Done | ||
8 | Start | LRDIMM_DB_MREP | |
9 | Done | ||
10 | Start | LRDIMM_DB_MRD_CYCLE | |
11 | Done | ||
12 | Start | LRDIMM_DB_MRD_CENTER | |
13 | Done | ||
14 | Start | LRDIMM_DB_DWL | |
15 | Done | ||
16 | Start | LRDIMM_DB_MWD_CYCLE | |
17 | Done | ||
18 | Start | LRDIMM_DB_MWD_CENTER | |
19 | Done | ||
20 | Start | DQS_GATE_CAL | |
21 | Done | ||
22 | Start | READ_DQ_CAL | |
23 | Done | ||
24 | Start | WRITE_LEVELING | |
25 | Done | ||
26 | Start | WRITE_DQ_DBI_CAL | |
27 | Done | ||
28 | Start | WRITE_LATENCY_CAL | |
29 | Done | ||
30 | Start | READ_DBI_CAL | |
31 | Done | ||
32 | Start | READ_DQ_VREF_CAL | |
33 | Done | ||
34 | Start | READ_DQ_DBI_CAL_COMPLEX | |
35 | Done | ||
36 | Start | WRITE_DQ_VREF_CAL | |
37 | Done | ||
38 | Start | WRITE_DQ_DBI_CAL_COMPLEX | |
39 | Done | ||
cal_r*_status | 40 | Start | EN_VT_TRACK |
41 | Done | ||
42 | Start | READ_DQS_TRACK | |
43 | Done |