DDR4 (x16) ROW_COLUMN_BANK_INTLV - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)
Document ID
PG353
Release Date
2023-10-18
Version
1.0 English
Table 1. DDR4 (x16) ROW_COLUMN_BANK_INTLV
SDRAM app_addr Mapping
Rank (RANK == 1) ? 1'b0:

app_addr[COL_WIDTH + ROW_WIDTH + BANK_WIDTH + BANK_GROUP_WIDTH +: RANK_WIDTH
Row app_addr[BANK_GROUP_WIDTH + BANK_WIDTH + COL_WIDTH +: ROW_WIDTH
Column app_addr[3 + BANK_GROUP_WIDTH + BANK_WIDTH + 1 +: COL_WIDTH - 4], app_addr[3 + BANK_GROUP_WIDTH + 1 +: 1, app_addr[2:0]
Bank app_addr[3 + BANK_GROUP_WIDTH + 2 +: BANK_WIDTH - 1], app_addr[3 + BANK_GROUP_WIDTH +: BANK_WIDTH - 1]
Bank Group app_addr[3 +: BANK_GROUP_WIDTH]
Table 2. DDR4 4 GB (256 MB x16) Single-Rank Mapping Example for ROW_COLUMN_BANK_INTLV
SDRAM Bus Row[14:0] Column[9:0] Bank[1:0] Bank Group
app_addr Bits 27 through 13 12 through 7, 5, and 2, 1, 0 6, 4 3