DM_DBI Parameter - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)
Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

The PHY supports the DDR4 DBI function on the read path and write path. The table shows how read and write DBI can be enabled separately or in combination.

When write DBI is enabled, Data Mask is disabled. The DM_DBI parameter only configures the PHY and the MRS parameters must also be set to configure the DRAM for DM/DBI.

Table 1. DM_DBI PHY Settings
DM_DBI Parameter Value PHY Read DBI PHY Write DBI PHY Write Data Mask
None Disabled Disabled Disabled
DM_NODBI Disabled Disabled Enabled
DM_DBIRD Enabled Disabled Enabled
NODM_DBIWR Disabled Enabled Disabled
NODM_DBIRD Enabled Disabled Disabled
NODM_DBIWRRD Enabled Enabled Disabled
NODM_NODBI Disabled Disabled Disabled

The allowed values for the DM_DBI option in the GUI are as follows for x8 and x16 parts (“✓” indicates supported and “–” indicates not supported):

Table 2. DM_DBI Options
Option Value Native AXI
ECC Disable ECC Enable ECC Disable ECC Enable
DM_NO_DBI 1 ✓ – ✓ –
DM_DBI_RD ✓ – ✓ –
NO_DM_DBI_RD ✓ ✓ – ✓
NO_DM_DBI_WR ✓ ✓ – ✓
NO_DM_DBI_WR_RD ✓ ✓ – ✓
NO_DM_NO_DBI 2 – ✓ – ✓
  1. Default option for ECC disabled interfaces.
  2. Default option for ECC enabled interfaces.

For x4 parts, the supported DM_DBI option value is "NONE."

DBI can be enabled to reduce power consumption in the interface by reducing the total number of DQ signals driven Low and thereby reduce noise in the VCCO supply. For more information on improved signal integrity, see AR 70006.