During DQS gate calibration for multi-rank systems, each rank is allowed to
calibrate independently given the algorithm as described in DQS Gate. After all ranks
have been calibrated, an adjustment is required before normal operation to ensure fast
rank-to-rank switching. The general interconnect signal clb2phy_rd_en
(indicated by DQS_GATE_READ_LATENCY_RANK_BYTE in XSDB) that controls the gate timing on
a DRAM-clock-cycle resolution is adjusted here to be the same for a given byte across
all ranks.
The coarse taps are adjusted so the timing of the gate opening stays the same
for any given rank, where four coarse taps are equal to a single read latency adjustment
in the general interconnect. During this step, the algorithm tries to find a common
clb2phy_rd_en setting where across all ranks for a given byte the
coarse setting would not overflow or underflow, starting with the lowest read latency
setting found for the byte during calibration. If the lowest setting does not work for
all ranks, the clb2phy_rd_en increments by one and the check is
repeated. The fine tap setting is < 90°, so it is not included in the adjustment.
If the check reaches the maximum clb2phy_rd_en
setting initially found during calibration without finding a value that works between
all ranks for a byte, an error is asserted. If after the adjustment is made and the
coarse taps are larger than 360° (four coarse tap settings), a different error is
asserted. For the error codes, see Error Signal Descriptions in the Error STATUS
section.
For multi-rank systems, the coarse taps must be seven or less so additional delay is added using the general interconnect read latency to compensate for the coarse tap requirement.