There are two types of debug signals used in Memory IP Versal adaptive SoC debug. The first set is a part of a debug interface that is always included in generated Memory IP Versal adaptive SoC designs. These signals include calibration status and tap settings that can be read at any time throughout operation when the Hardware Manager is open using either Tcl commands or the Memory IP Debug GUI.
The second type of debug signals are fully integrated in the IP when the Debug Signals option in the Memory IP tool is enabled and when using the Memory IP Example Design. These signals are brought up to the top-level and connected to a debug ILA core. These signals are documented in the following tables.