The XPHY is set up for write leveling by setting various attributes in the RIU. WL_TRAIN is set to decouple the DQS and DQ when driving out the DQS. This allows the XPHY to capture the returning DQ from the DRAM. Because the DQ is returned without the returning DQS strobe for capture, the RX_GATE is set to 0 in the XPHY to disable DQS gate operation.
DQS is delayed with ODELAY and coarse delay (WL_DLY_CRSE [12:9] applies to all bits in a nibble) provided in the RIU WL_DLY_RNKx register. The WL_DLY_FINE [8:0] location in the RIU is used to store the ODELAY value for write leveling for a given nibble (used by the XPHY when switching ranks).
A DQS train of pulses is output by the FPGA to the DRAM to detect the
relationship of CK and DQS at the DDR4 memory device. DQS is delayed using the coarse
taps in unit tap increments until a 0 to 1 transition is detected on the feedback DQ
input. Pattern 0X1 is searched after each coarse tap
increment for detecting the rising edge of CK.
If the algorithm never sees the pattern 0X1 using the coarse taps, the ODELAY of the DQS is set to an offset value
(first set at 45°, BRAM_WRLVL_OFFSET_RANK*_BYTE*) and the coarse taps are checked again
from 0 (the algorithm might need to perform this if the noise region is close to 90° or
there is a large amount of DCD). If the transition is still not found, the offset is
halved, and the algorithm tries again. If even after using all the ODELAY and coarse tap
it does not see the pattern 0X1 then write leveling
calibration error is issued.
The number of ODELAY taps used is determined by the initial alignment of the DQS and CK and the size of this noise region as shown in the figure.
After finding the rising edge of the CK, coarse tap is reverted back to the last stable 0 seen just before the rising edge and coarse tap value is saved as BRAM_WRLVL_CRSE_STG1_RANK*_BYTE*.