The search for the DQS begins with an estimate of when the DQS is expected back. The total latency for the read is a function of the delay through the PHY, PCB delay, and the configured latency of the DDR4 SDRAM (CAS latency, Additive latency, etc.). The search starts two DRAM clock cycles before the expected return of the DQS. The algorithm must start sampling before the first rising edge of the DQS, preferably in the preamble region. DDR4 preambles for the DQS is shown below.
To detect the third edge, a combination of the read latency and the coarse taps is used to add delay on the internal sampling clock signal. The delay is added until the third edge is detected for all the bytes. Delay update is masked for the byte group whose third edge of DQS is already detected.
The following figure shows an example of samples of a DQS burst with the expected sampling pattern to be found as the coarse taps are adjusted. The pattern is the expected level seen on the DQS over time as the sampling clock is adjusted in relation to the DQS.
Each individual element of the pattern is 32 read bursts from the DRAM
and samples from the XPHY. The gate in the XPHY is opened and a new sample is taken to
indicate the level seen on the DQS. If each of the samples matches with the first sample
taken, the value is accepted. If all samples are not the same value that value is marked
as X in the pattern. The X in the pattern shown is to allow for jitter and DCD between the clocks,
and to deal with uncertainty when dealing with clocks with an unknown alignment.
Depending on how the clocks line up they can resolve to all 0s, all 1s, or a mix of
values, and yet the DQS pattern can still be found properly.
The coarse taps in the XPHY are incremented and the value is recorded at each
individual coarse tap location, looking for the full pattern 000X1X0X1.
Detection of pattern 000X1X0X1 is equivalent to finding the third edge
of the DQS strobe.
If all allowable values of clb2phy_rd_en
for a given latency are checked and the expected pattern is still not found, the search
begins again from the start but this time the sampling is offset by an estimated 45°
using fine taps (half a coarse tap). This allows the sampling to occur at a different
phase than the initial relationship. Each time through if the pattern is not found, the
offset is reduced by half until all offset values have been exhausted.
The following figure shows an extreme case of DCD on the DQS that would result in the pattern not being found until an offset being applied using fine taps.
