Determining whether a data error is due to the write or the read can be difficult because if writes are the cause, read back of the data is bad as well. In addition, issues with control or address timing affect both writes and reads.
Some experiments that can help to isolate the issue include:
- If the errors are intermittent, issue a small initial number of writes, followed by continuous reads from those locations. If the reads intermittently yield bad data, there is a potential read issue. If the reads always yield the same (wrong) data, there is a write issue.
- Using high quality probes and scope, capture the write at the memory and the read at the FPGA to view data accuracy, appropriate DQS-to-DQ phase relationship, and signal integrity. To ensure the appropriate transaction is captured on DQS and DQ, look at the initial transition on DQS from 3-state to active. During a Write, DQS does not have a low preamble. During a read, the DQS has a low preamble.
- Analyze Read Timing:
- Check the PQTR/NQTR values after calibration. Look for variations between PQTR/NQTR values. PQTR/NQTR values should be very similar for DQs in the same DQS group.