The MC supports an optional SECDED ECC scheme that detects and corrects read data errors with 1-bit error per DQ bus burst and detects all 2-bit errors per burst. The 2-bit errors are not corrected. Three or more bit errors per burst might or might not be detected, but are never corrected. Enabling ECC adds four DRAM clock cycles of latency to all reads, whether errors are detected/corrected or not.
A Read-Modify-Write (RMW) scheme is also implemented to support Partial Writes
when ECC is enabled. Partial Writes have one or more user interface write data mask bits
set High. Partial Writes with ECC disabled are handled by sending the data mask bits to
the DRAM Data Mask (DM) pins, so the RMW flow is used only when ECC is enabled. When ECC
is enabled, Partial Writes require their own command, wr_bytes or
0x3, so the MC knows when to use the RMW flow.