The ECC module is instantiated inside the DDR4 Memory Controller. It is made up of five submodules as shown below.
Read data and check bits from the PHY are sent to the Decode block, and on the
next system clock cycle data and error indicators
ecc_single/ecc_multiple are sent to the NI.
ecc_single asserts when a correctable error is detected and the
read data has been corrected. ecc_multiple asserts when an
uncorrectable error is detected.
Read data is not modified by the ECC logic on an uncorrectable error. Error indicators are never asserted for “periodic reads,” which are read transactions generated by the controller only for the purposes of VT tracking and are not returned to the user interface or written back to memory in an RMW flow.
Write data is merged in the Encode block with read data stored in the ECC Buffer. The merge is controlled on a per byte basis by the write data mask signal. All writes use this flow, so full writes are required to have all data mask bits deasserted to prevent unintended merging. After the Merge stage, the Encode block generates check bits for the write data. The data and check bits are output from the Encode block with a one system clock cycle delay.
The ECC Gen block implements an algorithm that generates an H-matrix for ECC check bit generation and error checking/correction. The generated code depends only on the PAYLOAD_WIDTH and DQ_WIDTH parameters, where DQ_WIDTH = PAYLOAD_WIDTH + ECC_WIDTH. DQ_WIDTHs of 72, 40, and 24 with ECC_WIDTH of 8 are supported.