ECC Port Descriptions - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

The following table provides the ECC port descriptions at the User Interface.

Table 1. DDR4 ECC Operation Signal Direction Description
Signal I/O Description
ddr4_ecc_single[7:0] O The ddr4_ecc_single signal is non-zero if the read data from the external memory has a single bit error per beat of the read burst.
ddr4_ecc_multiple[7:0] O The ddr4_ecc_multiple signal is non-zero if the read data from the external memory has two bit errors per beat of the read burst. The SECDED algorithm does not correct the corresponding read data and puts a non-zero value on this signal to notify the corrupted read data at the User Interface.
ddr4_ecc_err_addr[51:0] O This bus contains the address of the current read command. The ddr4_ecc_err_addr signal is valid during the assertion of either ddr4_ecc_single or ddr4_ecc_multiple.