This register determines if the values of the CE_STATUS and UE_STATUS bits in the ECC Status register assert the Interrupt output signal (ECC_Interrupt). If both CE_EN_IRQ and UE_EN_IRQ are set to 1 (enabled), the value of the Interrupt signal is the logical OR between the CE_STATUS and UE_STATUS bits.
| Bits | Name | Core Access | Reset Value | Description |
|---|---|---|---|---|
| 1 | CE_EN_IRQ | R/W | 0 | If 1, the value of the CE_STATUS bit of ECC Status register is propagated to the Interrupt signal. If 0, the value of the CE_STATUS bit of ECC Status register is not propagated to the Interrupt signal. |
| 0 | UE_EN_IRQ | R/W | 0 | If 1, the value of the UE_STATUS bit of ECC Status register is propagated to the Interrupt signal. If 0, the value of the UE_STATUS bit of ECC Status register is not propagated to the Interrupt signal. |