The Error signal descriptions of host calibration stages in the Error Signal Descriptions table is true for LRDIMM host calibration stages, except that the stage numbering is as per LRDIMM dual-rank or quad-rank configuration.
The following table lists the error signals of the dual-rank LRDIMM data buffer calibration stages and their description.
| STAGE_NAME | Stage | Code | DDR_CAL_ERROR_1 | DDR_CAL_ERROR_0 | Error |
|---|---|---|---|---|---|
| Data Buffer Rank 0 MREP | 1 | 1 | Nibble | – | Edge 1 to 0 transition is not found for Rank 0 |
| Data Buffer Rank 0 MRD Cycle | 2 | 1 | Nibble | – | Pattern did not match for any of the Read latencies of Rank 0 |
| Data Buffer Rank 0 MRD Center | 3 | 1 | Nibble | – | Found very short read valid window for Rank 0 |
| Data Buffer Rank 0 DWL | 4 | 1 | Nibble | – | Edge 0 to 1 transition is not found for Rank 0 |
| Data Buffer Rank 0 MWD Cycle | 5 | 1 | Nibble | – | Pattern did not match for any of the Write latencies of Rank 0 |
| Data Buffer Rank 0 MWD Center | 6 | 1 | Nibble | – | Found very short write valid window for Rank 0 |
| Data Buffer Rank 1 MREP | 7 | 1 | Nibble | – | Edge 1 to 0 transition is not found for Rank 1 |
| Data Buffer Rank 1 MRD Cycle | 8 | 1 | Nibble | – | Pattern did not match for any of the Read latencies of Rank 1 |
| Data Buffer Rank 1 MRD Center | 9 | 1 | Nibble | – | Found very short read valid window for Rank 1 |
| Data Buffer Rank 1 DWL | 10 | 1 | Nibble | – | Edge 0 to 1 transition is not found for Rank 1 |
| Data Buffer Rank 1 MWD Cycle | 11 | 1 | Nibble | – | Pattern did not match for any of the Write latencies of Rank 1 |
| Data Buffer Rank 1 MWD Center | 12 | 1 | Nibble | – | Found very short write valid window for Rank 1 |
The following table lists the error signals of the quad-rank LRDIMM data buffer calibration stages and their description.
| STAGE_NAME | Stage | Code | DDR_CAL_ERROR_1 | DDR_CAL_ERROR_0 | Error |
|---|---|---|---|---|---|
| Data Buffer Rank 0 MREP | 1 | 1 | Nibble | – | Edge 1 to 0 transition is not found for Rank 0 |
| Data Buffer Rank 0 MRD Cycle | 2 | 1 | Nibble | – | Pattern did not match for any of the Read latencies of Rank 0 |
| Data Buffer Rank 0 MRD Center | 3 | 1 | Nibble | – | Found very short read valid window for Rank 0 |
| Data Buffer Rank 0 DWL | 4 | 1 | Nibble | – | Edge 0 to 1 transition is not found for Rank 0 |
| Data Buffer Rank 0 MWD Cycle | 5 | 1 | Nibble | – | Pattern did not match for any of the Write latencies of Rank 0 |
| Data Buffer Rank 0 MWD Center | 6 | 1 | Nibble | – | Found very short write valid window for Rank 0 |
| Data Buffer Rank 1 MREP | 7 | 1 | Nibble | – | Edge 1 to 0 transition is not found for Rank 1 |
| Data Buffer Rank 1 MRD Cycle | 8 | 1 | Nibble | – | Pattern did not match for any of the Read latencies of Rank 1 |
| Data Buffer Rank 1 MRD Center | 9 | 1 | Nibble | – | Found very short read valid window for Rank 1 |
| Data Buffer Rank 1 DWL | 10 | 1 | Nibble | – | Edge 0 to 1 transition is not found for Rank 1 |
| Data Buffer Rank 1 MWD Cycle | 11 | 1 | Nibble | – | Pattern did not match for any of the Write latencies of Rank 1 |
| Data Buffer Rank 1 MWD Center | 12 | 1 | Nibble | – | Found very short write valid window for Rank 1 |
| Data Buffer Rank 2 MREP | 13 | 1 | Nibble | – | Edge 1 to 0 transition is not found for Rank 2 |
| Data Buffer Rank 2 MRD Cycle | 14 | 1 | Nibble | – | Pattern did not match for any of the Read latencies of Rank 2 |
| Data Buffer Rank 2 MRD Center | 15 | 1 | Nibble | – | Found very short read valid window for Rank 2 |
| Data Buffer Rank 2 DWL | 16 | 1 | Nibble | – | Edge 0 to 1 transition is not found for Rank 2 |
| Data Buffer Rank 2 MWD Cycle | 17 | 1 | Nibble | – | Pattern did not match for any of the Write latencies of Rank 2 |
| Data Buffer Rank 2 MWD Center | 18 | 1 | Nibble | – | Found very short write valid window for Rank 2 |
| Data Buffer Rank 3 MREP | 19 | 1 | Nibble | – | Edge 1 to 0 transition is not found for Rank 3 |
| Data Buffer Rank 3 MRD Cycle | 20 | 1 | Nibble | – | Pattern did not match for any of the Read latencies of Rank 3 |
| Data Buffer Rank 3 MRD Center | 21 | 1 | Nibble | – | Found very short read valid window for Rank 3 |
| Data Buffer Rank 3 DWL | 22 | 1 | Nibble | – | Edge 0 to 1 transition is not found for Rank 3 |
| Data Buffer Rank 3 MWD Cycle | 23 | 1 | Nibble | – | Pattern did not match for any of the Write latencies of Rank 3 |
| Data Buffer Rank 3 MWD Center | 24 | 1 | Nibble | – | Found very short write valid window for Rank 3 |