EXTRA_CMD_DELAY Parameter - 1.0 English

Depending on the number of ranks, ECC mode, and DRAM latency configuration, PHY must be programmed to add latency on the DRAM command address bus. This provides enough pipeline stages in the PHY programmable logic to close timing and to process mcWrCAS. Added command latency is generally needed at very low CWL in single-rank configurations, or in multi-rank configurations. Enabling ECC might also require adding command latency, but this depends on whether your controller design (outside the PHY) depends on receiving the wrDataEn signal a system clock cycle early to allow for generating ECC check bits.

The EXTRA_CMD_DELAY parameter is used to add one or two system clock cycles of delay on the DRAM command/address path. The parameter does not delay the mcWrCAS or mcRdCAS signals. This gives the PHY more time from the assertion of mcWrCAS or mcRdCAS to generate XPHY control signals. To the PHY, an EXTRA_CMD_DELAY setting of one or two is the same as having a higher CWL or AL setting.

The table shows the required EXTRA_CMD_DELAY setting for various configurations of CWL, CL, and AL.