After the DQS gate multi-rank adjustment (if required), a signal is sent to the
XPHY to recalibrate internal delays to start voltage and temperature tracking. The XPHY
asserts a signal when complete, phy2clb_phy_rdy_upp for upper nibbles
and phy2clb_phy_rdy_low for lower nibbles.
For multi-rank systems, when all nibbles are ready for normal operation there is
a requirement of the XPHY where two write-read bursts are required to be sent to the
DRAM before starting normal traffic. A data pattern of F00FF00F is used for the first and 0FF00FF0 for the second. The data itself is not checked and is expected to
fail.