Error Address - 1.0 English

Each time a read CAS command is issued, the full DRAM address is stored in a FIFO in the decode block. When read data is returned and checked for errors, the DRAM address is popped from the FIFO and ecc_err_addr[51:0] is returned on the same cycle as signals ecc_single and ecc_multiple for the purposes of error logging or debug. The following table is a common definition of this address for DDR4.