Example Design - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

Generation of a DDR4 design through the Memory IP tool allows an example design to be generated using the Vivado Generate IP Example Design feature. The example design includes a synthesizable test bench with a traffic generator that is fully verified in simulation and hardware. This example design can be used to observe the behavior of the Memory IP design and can also aid in identifying board-related problems.

For complete details on the example design, see Example Design chapter. The following sections describe using the example design to perform hardware validation.