- Look at the individual BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE*, BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT* and BRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE* tap settings. The taps should only vary by 0 to 20 taps. To calculate the write window, see Determining Window Size in ps section.
- Determine if any bytes completed successfully. The write calibration algorithm steps through each DQS byte group detecting the capture edges.
- If the incorrect data pattern is detected, determine if the error is due to the write access or the read access. See Determining If a Data Error is Due to the Write or Read.
- Both edges need to be found. This is possible at all frequencies because the algorithm uses 90° of ODELAY taps to find the edges.
- To analyze the window size in ps, see Determining Window Size in ps section. As a general rule of thumb, the window size for a healthy system should be ≥ 30% of the expected UI size.