This register is used to inject errors in the generated ECC written to the memory and can be used to test the error correction and error signaling. The bits set in the register toggle the corresponding ECC bits of the next data written to memory. After the fault has been injected, the Fault Injection ECC register is cleared automatically.
The register is only implemented if C_ECC_TEST = ON or ECC_TEST_FI_XOR = ON and ECC = ON in a DDR4 SDRAM design in the Vivado IP catalog.
Injecting faults should be performed in a critical region in software; that is, writing this register and the subsequent write to memory must not be interrupted.
The table describes the register bit usage when DQ_WIDTH = 72.
Bits | Name | Core Access | Reset Value | Description |
---|---|---|---|---|
7:0 | FI_ECC | W | 0 | Bit positions set to 1 toggle the corresponding bit of the next ECC written to the memory. The register is automatically cleared after the fault has been injected. |
The table describes the register bit usage when DQ_WIDTH = 144.
Bits | Name | Core Access | Reset Value | Description |
---|---|---|---|---|
15:0 | FI_ECC | R | 0 | Bit positions set to 1 toggle the corresponding bit of the next ECC written to the memory. The register is automatically cleared after the fault has been injected. |