In this section, the ATG basic feature support and mode of operation is described. The ATG allows you to program different traffic patterns, read-write mode, and the duration of traffic burst based on their application.
The ATG provides one traffic pattern for a simple traffic test in the direct instruction mode or program up to 32 traffic patterns into the traffic pattern table for a regression test in the traffic table mode.
Each traffic pattern can be programmed with the following options:
- Address Mode
- Linear, PRBS, walking1/0.
- Data Mode
- Linear, PRBS 8/10/23, walking1/0, and hammer1/0.
- Read/Write Mode
- Write-read, write-only, read-only, write-once-read-forever.
- Read/Write Submode
- When read/write mode is set to write-read, you can choose how to send write and read commands. The first choice sends all write commands follow by read commands. The second choice sends write and read command pseudo-randomly.
- Victim Mode
- No Victim, held1, held0, non-inverted aggressor, inverted aggressor, delayed aggressor, delayed victim.
- Victim Aggressor Delay
- Victim or aggressor delay when the Victim mode of "delayed aggressor" or "delayed victim" modes is used.
- Victim Select
- Victim selected from the ATG VIO input or victim rotates per nibble/per byte/per interface width.
- Number of Command Per Traffic Pattern
- Number of command per traffic pattern.
- Number of NOPs After Bursts
- Number of NOPs after bursts.
- Number of Bursts Before NOP
- Number of bursts before NOP.
- Next Instruction Pointer
- Next instruction pointer.
You can create one traffic pattern for simple traffic test using the direct
instruction mode (vio_tg_direct_instr_en) or create a
sequence of traffic patterns by programming a "next instruction" (vio_tg_instr_nxt_instr) pointer pointing to one of the 32
traffic pattern entries for regression test in traffic table mode.
The example in the following table shows four traffic patterns programmed in the table mode.
| Instruction Number | Addr Mode | Data Mode | Read/Write Mode | Victim Mode | Number of Instruction Iteration | Insert M NOPs between N-Burst (M) | Insert M NOPs between N-Burst (N) | Next Instruction |
|---|---|---|---|---|---|---|---|---|
| 0 | Linear | PRBS | Write-Read | No Victim | 1,000 | 20 | 100 | 1 |
| 1 | Linear | PRBS | Write-Read | No Victim | 1,000 | 0 | 500 | 2 |
| 2 | Linear | Linear | Write-Only | No Victim | 10,000 | 10 | 100 | 3 |
| 3 | Linear | Walking1 | Write-Read | No Victim | 1,000 | 10 | 100 | 0 |
| ... | ||||||||
| 31 |
The first pattern has PRBS data traffic written in Linear address space. The 1,000 write commands are issued followed by 1,000 read commands. Twenty cycles of NOPs are inserted between every 100 cycle of commands. After completion of instruction0, the next instruction points at instruction1.
Similarly, instruction1, instruction2, and instruction3 is executed and then looped back to instruction0
The ATG waits for calibration to complete (init_calib_complete and tg_startassertion). After the calibration complete and assertion of tg_start, the ATG starts sending the default traffic
sequence according to traffic pattern table or direct instruction programmed. Memory
Read/Write requests are then sent through the application interface, Memory Controller,
and PHY. Either program the instruction table before asserting tg_start or pause the traffic generator (by asserting vio_tg_pause), reprogram the instruction table, and
restart the test traffic for custom traffic pattern. For more information, see the
following Usage section.
The ATG performs error check when a traffic pattern is programmed to read/write modes that have write requests followed by read request (that is, Write-read-mode or Write-once-Read-forever-mode). The ATG first sends all write requests to the memory. After all write requests are sent, the ATG sends read requests to the same addresses as the write requests. Then the read data returning from memory is compared with the expected read data.
If there is no mismatch error and the ATG is not programmed into an infinite loop,
vio_tg_status_done asserts to indicate run completion
The ATG has watchdog logic. The watchdog logic checks if the ATG has any request sent to the application interface or the application interface has any read data return within N (parameter TG_WATCH_DOG_MAX_CNT) number of cycles. This provides information on whether memory traffic is running or stalled (because of reasons other than data mismatch).