| General Control | I/O | Width | Description |
|---|---|---|---|
| vio_tg_start | I | 1 | Enable traffic generator to
proceed from "START" state to "LOAD" state after calibration
completes. If you do not plan to program
instruction table NOR PRBS data seed, tie this signal to If you plan to program instruction table OR PRBS data seed, set this bit to 0 during reset. After reset deassertion and done with instruction/seed programming, set this bit to 1 to start traffic generator. |
| vio_tg_rst | I | 1 | Reset traffic generator (synchronous reset, level sensitive). If there is outstanding traffic in memory pipeline, assert this signal long enough until all outstanding transactions have completed. |
| vio_tg_restart | I | 1 | Restart traffic generator after
traffic generation is complete, paused, or stopped with error (level
sensitive). If there is outstanding traffic in memory pipeline, assert this signal long enough until all outstanding transactions have completed. |
| vio_tg_pause | I | 1 | Pause traffic generator (level sensitive) |
| vio_tg_err_chk_en | I | 1 | If enabled, stop upon first error detected. Read test is performed to determine whether "READ" or "WRITE" error occurred. If not enabled, continue traffic without stop. |
| vio_tg_err_clear | I | 1 | Clear all errors excluding sticky error bit (positive edge sensitive). Only use this signal when vio_tg_status_state is either TG_INSTR_ERRDONE or TG_INSTR_PAUSE. |
| vio_tg_err_clear_all | I | 1 | Clear all errors including sticky error bit (positive edge sensitive). Only use this signal when vio_tg_status_state is either TG_INSTR_ERRDONE or TG_INSTR_PAUSE. |
| vio_tg_err_continue | I | 1 | Continue traffic after error(s) at TG_INSTR_ERRDONE state (positive edge sensitive). |