Hardware Measurements - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)
Document ID
PG353
Release Date
2023-10-18
Version
1.0 English
  1. If the write complex pattern fails, use high quality probes and scope the DQS-to-DQ phase relationship at the memory during a write. Trigger at the start (cal_r*_status[38] = R for Rising Edge) and again at the end (cal_r*_status[39] = R for Rising Edge) of Write Complex DQS Centering to view the starting and ending alignments. The alignment should be approximately 90°.
  2. If the DQS-to-DQ alignment is correct, observe the we_n-to-DQS relationship to see if it meets CWL again using cal_r*_status[25] = R for Rising Edge as a trigger.
  3. For all stages of write/read leveling, probe the write commands and read commands at the memory:
    • Write = cs_n = 0; ras_n = 1; cas_n = 0; we_n = 0; act_n = 1
    • Read = cs_n = 0; ras_n = 1; cas_n = 0; we_n = 1; act_n = 1
  4. Using theVivado Hardware Manager and while running the Memory IP Example Design with the Debug Signals enabled, set the trigger (cal_r*_status[38] = R for Rising Edge). The following simulation example shows how the debug signals should behave during successful Write DQS-to-DQ.
Figure 1. Expected Behavior during Write Complex Pattern Calibration