Instruction Programming - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)
Document ID
PG353
Release Date
2023-10-18
Version
1.0 English
Table 1. Instruction Programming
Instruction Programming I/O Width Description
vio_tg_direct_instr_en I 1 0: Traffic Table Mode – Traffic Generator uses traffic patterns programmed in 32-entry traffic table.

1: Direct Instruction Mode – Traffic Generator uses current traffic pattern presented at VIO interface.
vio_tg_instr_program_en I 1 Enable instruction table programming (level sensitive)
vio_tg_instr_num I 5 Instruction number to be programmed
vio_tg_instr_addr_mode I 4 Address mode to be programmed.
  • 0: LINEAR (with user defined start address)
  • 1: PRBS (PRBS supported range from 8 to 34 based on address width)
  • 2: WALKING1
  • 3: WALKING0
  • [4:15]: Reserved
vio_tg_instr_data_mode I 4 Data mode to be programmed.
  • 0: LINEAR
  • 1: PRBS (PRBS supported 8, 10, 23)
  • 2: WALKING1
  • 3: WALKING0
  • 4: HAMMER1
  • 5: HAMMER0
  • 6: Block RAM
  • 7: CAL_CPLX (Must be programmed along with victim mode CAL_CPLX)
  • [8:15]: Reserved
vio_tg_instr_rw_mode I 4
  • 0: Read Only (No data check)
  • 1: Write Only (No data check)
  • 2: Write / Read (Read performs after Write and data value is checked against expected write data)
  • 3: Write Once and Read forever (Data check on Read data)
  • [4:15]: Reserved
vio_tg_instr_rw_submode I 2 Read/Write sub-mode to be programmed.

This is a sub-mode option when vio_tg_instr_rw_mode is set to "WRITE_READ" mode

  • 0: WRITE_READ (Send all Write commands follow by Read commands defined in the instruction)
  • 1: WRITE_READ_SIMULTANEOUSLY (Send Write and Read commands pseudo-randomly)
    Note: Write is always ahead of Read.
  • [2:3] : Reserved
vio_tg_instr_victim_mode I 3 Victim mode to be programmed.

One victim bit could be programmed using global register vio_tg_victim_bit. The rest of the bits on signal bus are considered to be aggressors.

The following program options define aggressor behavior:

  • 0: NO_VICTIM
  • 1: HELD1 (All aggressor signals held at 1)
  • 2: HELD0 (All aggressor signals held at 0)
  • 3: NONINV_AGGR (All aggressor signals are same as victim)
  • 4: INV_AGGR (All aggressor signals are inversion of victim)
  • 5: DELAYED_AGGR (All aggressor signals are delayed version of victim. Number of cycle of delay is programmed at vio_tg_victim_aggr_delay)
  • 6: DELAYED_VICTIM (Victim signal is delayed version of all aggressors)
  • 7: CAL_CPLX (Complex Calibration pattern must be programed along with Data Mode CAL_CPLX)
vio_tg_instr_victim_aggr_delay I 5 Define aggressor/victim pattern to be N-delay cycle of victim/aggressor.

It is used when victim mode "DELAY_AGGR" or "DELAY VICTIM" mode is used in traffic pattern
vio_tg_instr_victim_select I 3 Victim bit behavior programmed.
  • 0: VICTIM_EXTERNAL (Use Victim bit provided in vio_tg_glb_victim_bit)
  • 1: VICTIM_ROTATE4 (Victim bit rotates from Bit[0] to Bit[3] for every Nibble)
  • 2: VICTIM_ROTATE8 (Victim bit rotates from Bit[0] to Bit[7] for every byte)
  • 3: VICTIM_ROTATE_ALL (Victim bit rotates through all bits)
  • [4:7]: Reserved
vio_tg_instr_num_of_iter I 32 Number of Read/Write commands to issue (number of issue must be > 0 for each instruction programmed)
vio_tg_instr_m_nops_btw_n_burst_m I 10 M: Number of NOP cycles in between Read/Write commands at User interface at general interconnect clock.

N: Number of Read/Write commands before NOP cycle insertion at User interface at general interconnect clock.
vio_tg_instr_m_nops_btw_n_burst_n I 32 M: Number of NOP cycles in between Read/Write commands at User interface at general interconnect clock.

N: Number of Read/Write commands before NOP cycle insertion at User interface at general interconnect clock.
vio_tg_instr_nxt_instr I 6 Next instruction to run.

To end traffic, next instruction should point at EXIT instruction.

  • 6’b000000-6’b011111 – valid instruction
  • 6’b1????? – EXIT instruction