The AMD Versal™ adaptive SoC Memory IP core is a combined pre-engineered controller and physical layer (PHY) for interfacing Versal adaptive SoC user designs to DDR4 SDRAM devices.
The AMD Versal™ adaptive SoC Memory IP core is a combined pre-engineered controller and physical layer (PHY) for interfacing Versal adaptive SoC user designs to DDR4 SDRAM devices.