This training aligns the Write MDQS phase with the DRAM clock. In this training mode, the data buffer drives the MDQS pulses, the DRAM samples the clock with MDQS and feeds back the result on MDQ. The data buffer forwards this result from MDQ to DQ. Calibration continues to perform this training to find a 0 to 1 transition on the clock sampled with the Write MDQS at the DRAM.
| XSDB Reg | Usage | Signal Description |
|---|---|---|
| BRAM_DB_DWL_MWD_LAT_RANK*_NIBBLE* | One value per rank per nibble | Data Buffer phase [8:6] and Data Buffer to DRAM latency [5:0] |