LRDIMM MREP Training - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

MREP training aligns the Read MDQS phase with the data buffer clock. In this training mode, the memory controller sends a sequence of read commands, the DRAM sends out the MDQS, the data buffer samples the strobe with the clock and feeds the result back on DQ. Calibration continues to perform this training to find the 0 to 1 transition on the Read MDQS sampled with the data buffer clock.

Table 1. MREP Training Register
XSDB Reg Usage Signal Description
BRAM_DB_MREP_MRD_LAT_RANK*_NIBBLE* One value per rank per nibble MRD latency [8:6] and MREP phase [5:0]