MRD Cycle Training - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

This training is to find out the correct cycle to maintain the set Read Latency value at the data buffer. In this training mode, host pre-programs the DB MPR registers with the expected pattern and issues the read commands. Data buffer compares the read data with the expected data and feeds the result on to the DQ bus. Calibration picks up the correct cycle based on the result of the comparison.