Memory IP Debug GUI Usage - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

After configuring the device, the Memory IP debug core and contents are visible in the Hardware Manager (see figure).

Figure 1. Memory IP Debug Properties and Configuration Windows

To export information about the properties to a spreadsheet, see the figure below which shows the Memory IP Core Properties window. Under the Properties view, right-click anywhere in the field, and select the Export to Spreadsheet... option in the context menu. Select the location and name of the file to save, use all the default options, and then click OK to save the file.

For more information on the Properties window menu commands, see the “Properties Window Popup Menu Commands” section in the Vivado Design Suite User Guide: Getting Started (UG910).

Figure 2. Memory IP Core Properties Export to Spreadsheet
Figure 3. Example Display of Memory IP Debug Core
Figure 4. Example of Refresh Device