Memory IP Debug Tcl Usage - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

The following Tcl commands are available from the AMD Vivado™ Tcl Console when connected to the hardware.

This outputs all XSDB Memory IP content that is displayed in the GUIs.
get_hw_softmcs
Displays what Soft Memory IP cores exist in the design
refresh_hw_device
Refreshes the whole device including all cores
refresh_hw_mig [lindex [get_hw_softmcs] 0]
Refreshes only the Memory IP core denoted by index (index begins with 0)
report_property [lindex [get_hw_softmcs] 0]
Reports all of the parameters available for the Memory IP core. Where 0 is the index of the Memory IP core to be reported (index begins with 0).
report_debug_core
Reports all debug core peripherals connected to the Debug Hub (dbg_hub). Associates the debug core "Index" with the "Instance Name." Useful when multiple instances of Memory IP are instantiated within the design to associate the debug core index with the each IP instantiation.

report_debug_core example:

Peripherals Connected to Debug Hub “dbg_hub” (2 Peripherals):
+-------+------------------------------+----------------------------------+
| Index | Type | Instance Name |
+-------+------------------------------+----------------------------------+
| 0 | vio_v3_0 | gtwizard_ultrascale_0_vio_0_inst |
+-------+------------------------------+----------------------------------+
| 1 | labtools_xsdb_slave_lib_v2_1 | your_instance_name |
+-------+------------------------------+----------------------------------+
| 2 | labtools_xsdb_slave_lib_v2_1 | your_instance_name |
+-------+------------------------------+----------------------------------+
| 3 | labtools_xsdb_slave_lib_v2_1 | your_instance_name |
+-------+------------------------------+----------------------------------+
| 4 | labtools_xsdb_slave_lib_v2_1 | your_instance_name |
+-------+------------------------------+----------------------------------+