To focus the debug of calibration or data errors, use the provided Memory IP example design on the targeted board with the Debug Feature enabled through the Memory IP AMD Versal™ adaptive SoC GUI.
Note: Using the Memory IP
example design and enabling the Debug
Feature is not required to capture calibration and window
results using XSDB, but it is useful to focus the debug on a known working
solution.
However, the debug signals and example design are required to analyze the provided Integrated Logic Analyzer (ILA) and VIO debug signals within the Vivado Design Suite debug feature. The latest Memory IP release should be used to generate the example design.