Memory Initialization and Calibration Sequence

Memory Initialization and Calibration Sequence - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID

PG353

Release Date

2023-10-18

Version

1.0 English

After deassertion of the system reset, the PHY performs some required internal calibration steps first.

The built-in self-check (BISC) of the PHY is run. BISC is used in the PHY to compute internal skews for use in voltage and temperature tracking after calibration is completed.
After BISC is completed, calibration logic performs the required power-on initialization sequence for the memory.
This is followed by several stages of timing calibration for the write and read datapaths.
After calibration is completed, the PHY calculates internal offsets to be used in voltage and temperature tracking.
The PHY indicates calibration is finished and the controller begins issuing commands to the memory.

The following table shows the overall flow of memory initialization and the different stages of calibration.

Table 1. PHY Overall Initialization and Calibration Sequence
Serial Number	Calibration Stage	Calibration Stage Code	DDR4	DDR4_LRDIMM	Rank-wise Calibration
1	PHY Related calibration	0x0	Yes	Yes	N/A
2	Memory Initialization (DDR4, RCD, DB as applicable)	0x1	Yes	Yes	N/A
3	LRDIMM Data Buffer MREP Training	0x2	N/A	Yes	Sequential
4	LRDIMM Data Buffer MRD Cycle Training	0x3	N/A	Yes	Sequential
5	LRDIMM Data Buffer MRD Center Training	0x4	N/A	Yes	Sequential
6	LRDIMM Data Buffer DWL Training	0x5	N/A	Yes	Sequential
7	LRDIMM Data Buffer MWD Cycle Training	0x6	N/A	Yes	Sequential
8	LRDIMM Data Buffer MWD Center Training	0x7	N/A	Yes	Sequential
9	DQS Gate Calibration	0x8	Yes	Yes	Sequential
10	Write Leveling	0x9	Yes	Yes	Sequential
11	Read DQ per-bit deskew and centering: Simple	0xA	Yes	Yes	Parallel
12	Write DQ/DBI per-bit deskew and centering: Simple	0xB	Yes	Yes	Parallel
13	Write Latency calibration	0xC	Yes	Yes	Sequential
14	Read DBI deskew and centering: Simple	0xD	Yes	Yes	Parallel
15	Read DQ V_REF training	0xE	Yes	Yes	Parallel
16	Read DQS-DQ/DBI centering: Complex	0xF	Yes	Yes	Parallel
17	Write DQ V_REF training	0x10	Yes	Yes	Sequential
18	Write DQS-DQ/DBI centering: Complex	0x11	Yes	Yes	Parallel
19	Enable VT Tracking	0x12	Yes	Yes	N/A
20	Read DQS Tracking adjustment calibration	0x13	Yes	Yes	Parallel
21	Calibration Done	0x14	Yes	Yes	N/A
Sequential (Rank-wise Calibration): This means that the calibration stage will be completed one rank at a time in sequence. Parallel (Rank-wise Calibration): This means that the calibration stage will be performed for all ranks simultaneously.

For LRDIMM configuration, the Data Buffer (DB) acts as an endpoint and represents all the ranks of the LRDIMM card. Hence all calibration stages are performed between the Host and the Data buffer.

Not all configurations require the entire calibration sequence to be performed. There will be variations to this sequence based on data rate. The hardware manager will list the actual calibration sequence for the configuration being used.

When simulating a design out of DDR4 SDRAM, the calibration it set to be bypassed to enable you to generate traffic to and from the DRAM as quickly as possible. When running in hardware or simulating with calibration, signals are provided to indicate the calibration stage being performed and the error status per stage.