The minimum Write CAS to Write CAS command spacing to different ranks is eight
DRAM clocks. This is a PHY limitation. If you violate this timing, the PHY might not
have enough time to switch its internal delay settings and drive Write
DQ
/DQS
on the DDR bus with correct timing. The
internal delay settings are determined during calibration, and it varies with system
layout.
Following the memory system layout guidelines ensures that a spacing of eight DRAM clocks is sufficient for correct operation. Write to Write timing to the same rank is limited only by the DRAM specification and the command slot limitations for CAS commands discussed earlier.