Multi-Rank Adjustment - 1.0 English

For multi-rank systems, separate control exists in the XPHY for each rank and every rank can be trained separately for coarse and fine taps. After all ranks have been calibrated, an adjustment is required before normal operation to ensure fast rank-to-rank switching.

Across all ranks within a byte, the read latency and general interconnect delay (clb2phy_rd_en) must match. The coarse taps are incremented/decremented accordingly to adjust the timing of the gate signal to match the timing found in calibration. If a common clb2phy_rd_en setting cannot be found for a given byte across all ranks, an error is asserted. Additionally, the coarse taps have to be within four taps within the same byte lane across all ranks. The following table shows the DQS Gate adjustment examples.