The fine taps are incremented until a non-zero value is returned. This is recorded as the left edge of the unstable region (BRAM_WRLVL_FINE_LEFT_RANK*_BYTE*). The fine taps are incremented again until all samples taken return a 1. This is recorded as the right edge of the uncertain region (BRAM_WRLVL_FINE_RIGHT_RANK*_BYTE*). Various write leveling regions are shown in the figure.
After finding both the edges of the noise region, DQS is centered in the noise region. The final fine tap is computed as the midpoint of the uncertain region, odelay – MIN_VALID_CNT – ((right_edge_taps – left_edge_taps) / 2).
After the final ODELAY setting is found, the value of ODELAY is loaded in the RIU in the WL_DLY_RNKx[8:0] register and BRAM_WRLVL_FINE_FINAL_RANK*_BYTE*. This value is also loaded in the ODELAY register for the DQ and the DM to match the DQS.
After write leveling, the MPR command is sent to the DRAM to disable the write leveling feature, the WL_TRAIN is set back to the default OFF setting, and the DQS gate is turned back on to allow for capture of the DQ with the returning strobe DQS.