The Versal adaptive SoC PHY is composed of dedicated blocks and soft calibration logic. The dedicated blocks are structured adjacent to one another with back-to-back interconnects to minimize the clock and datapath routing necessary to build high performance physical layers.
The MC and calibration logic communicate with this dedicated PHY in the slow frequency clock domain, which is either divided by four or divided by two. This depends on the DDR4 memory clock. A more detailed block diagram of the PHY design is shown in the following figure.
The MC is designed to separate out the command processing from the low-level PHY requirements to ensure a clean separation between the controller and physical layer. The command processing can be replaced with custom logic if desired, while the logic for interacting with the PHY stays the same and can still be used by the calibration logic.
Module Name | Description |
---|---|
<module>_...cal_top.sv | Contains <module>_...cal_top.sv, <module>_...mc_pi.sv, and MUXes between the calibration and the Memory Controller. |
<module>_...cal_riu.sv | Contains the MicroBlaze processing system and associated logic. |
<module>_...mc_pi.sv | Adjusts signal timing for the PHY for reads and writes. |
<module>_...cal_addr_decode.sv | Versal adaptive SoC logic interface for the MicroBlaze processor. |
<module>_...config_rom.sv | Configuration storage for calibration options. |
microblaze_mcs_0.sv | MicroBlaze MCS module |
<module>_...iob.sv | Instantiates all byte IOB modules. |
<module>_...iob_byte.sv | Generates the I/O buffers for all the signals in a given byte lane. |
<module>_...debug_microblaze.sv | Simulation-only file to parse debug statements from software running in MicroBlaze to indicate status and calibration results to the log. |
<module>_...cal_cplx.sv | RTL state machine for complex pattern calibration. |
<module>_...cal_cplx_data.sv | Data patterns used for complex pattern calibration. |
<module>_...xphy.sv | Top-level XPHY module. |
<module>_...phy.sv | Top-level of the PHY, contains pll and xphy.sv modules. |
The PHY architecture encompasses all of the logic contained in <module>_...phy.sv. The PHY contains wrappers around dedicated hard blocks to build up the memory interface from smaller components. A byte lane contains all of the clocks, resets, and datapaths for a given subset of I/O. Multiple byte lanes are grouped together, along with dedicated clocking resources, to make up a single bank memory interface. Each nibble in the PHY contains a Register Interface Unit (RIU), a dedicated integrated block in the XPHY that provides an interface to the general interconnect logic for changing settings and delays for calibration. For more information on the hard silicon physical layer architecture, see the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).
The memory initialization is executed in Verilog RTL. The calibration and training are implemented by an embedded MicroBlaze™ processor. The MicroBlaze Controller System (MCS) is configured with an I/O Module and a block RAM. The <module>_...cal_addr_decode.sv module provides the interface for the processor to the rest of the system and implements helper logic. The <module>_...config_rom.sv module stores settings that control the operation of initialization and calibration, providing run time options that can be adjusted without having to recompile the source code.
The address unit connects the MCS to the local register set and the PHY by performing address decode and control translation on the I/O module bus from spaces in the memory map and MUXing return data (<module>_...cal_addr_decode.sv). In addition, it provides address translation (also known as “mapping”) from a logical conceptualization of the DRAM interface to the appropriate pinout-dependent location of the delay control in the PHY address space.
Although the calibration architecture presents a simple and organized address map for manipulating the delay elements for individual data, control and command bits, there is flexibility in how those I/O pins are placed. For a given I/O placement, the path to the Versal adaptive SoC logic is locked to a given pin. To enable a single binary software file to work with any memory interface pinout, a translation block converts the simplified RIU addressing into the pinout-specific RIU address for the target design (see Table 2).
The specific address translation is written by DDR4 SDRAM after a pinout is selected and cannot be modified. The code shows an example of the RTL structure that supports this.
Casez(io_address) // MicroBlaze I/O module address
// ... static address decoding skipped
//========================================//
//===========DQ ODELAYS===================//
//========================================//
//Byte0
28’h0004100: begin //c0_ddr4_dq[0] IO_L20P_T3L_N2_AD1P_44
riu_addr_cal = 6’hD;
riu_nibble = ‘h6;
end
// ... additional dynamic addressing follows
In this example, DQ0
is pinned out on Bit[0] of nibble 0
(nibble 0 according to instantiation order). The RIU address for the ODELAY for Bit[0]
is 0x0D
. When DQ0
is addressed —
indicated by address 0x000_4100
), this snippet of code
is active. It enables nibble 0 (decoded to one-hot downstream) and forwards the address
0x0D
to the RIU address bus.
The MicroBlaze I/O module interface is not always fast enough for implementing all of the functions required in calibration. A helper circuit implemented in <module>_...cal_addr_decode.sv is required to obtain commands from the registers and translate at least a portion into single-cycle accuracy for submission to the PHY. In addition, it supports command repetition to enable back-to-back read transactions and read data comparison.
RIU Address | Name | Description |
---|---|---|
0x00 | NIBBLE_CTRL0 | Nibble Control 0: Controls nibble clocking from neighboring nibble, inversion of clock path from IOB to RX Bitslice-0, serial mode for IOB pair, transmit clock gating, receive clock gating, preamble extension for DQS_BIAS, fixdly_rdy generation, clearing gate for BISC, and disabling RX bitslice dynamic mode. |
0x01 | NIBBLE_CTRL1 | Nibble Control 1: Controls 90° phase shift of RX clock , TX clock per bitslice, tristate output, RefClk TX bitslice, and Reference data Xx bitslice. |
0x02 | CALIB_CTRL | Calibration Control: Controls BISC calibration,
IDELAY BISC VT tracking, ODELAY BISC VT tracking, BISC calibration per
bitslice and Master clock bitslice when IDELAY or ODELAY set to
TIME. Provides status of fixed delay calibration and PHY ready, state of BS_RESET_CTRL.bsc_reset, controls PQTR and NQTR VT tracking, and indicates status of BISC state machine. |
0x03 | BS_RESET_CTRL | Bitslice reset control: Controls clear gate, bitslice
reset, bitslice-tri reset, and monitor reset if not masked. Also, it
controls software BISC reset and XPHY reset when set by DDRMC (must
assert for a minimum of 8 RIU clock cycles). Provides gate status, indicates overflow and underflow of coarse delay. |
0x05 | IODLY_BCAST_MASK | Broadcast IDELAY and ODELAY mask |
0x06 | IODLY_BCAST_CTRL | IO delay broadcast control: Enable/Disable IDELAY and ODELAY broadcast, controls fine or coarse increment or decrement or self clear when not masked. |
0x07 | PQTR | Rising edge delay for DQS: Controls one tap increment/decrement, or coarse increment/decrement. |
0x08 | NQTR | Falling edge delay for DQS: Controls one tap increment/decrement or coarse increment/decrement. |
0x09 | MON | Monitor delay: Controls one tap or coarse increments/decrements. |
0x0A | TRISTATE_ODLY | Bitslice-tri delay: Controls one tap or coarse increments/decrements. |
0x0B | ODLY0 | Bitslice-0 odelay: Controls one tap increments/decrements or coarse increments/decrements based on CntvalueIn. Wraps around to h'0 when incremented at delay value h'3ff. Wraps around to h`3ff when decremented at delay value h`0. |
0x0C | ODLY1 | Bitslice-1 odelay: Controls one tap increments/decrements or coarse increments/decrements based on CntvalueIn. Wraps around to h'0 when incremented at delay value h'3ff. Wraps around to h`3ff when decremented at delay value h`0. |
0x0D | ODLY2 | Bitslice-2 odelay: Controls one tap increments/decrements or coarse increments/decrements based on CntvalueIn. Wraps around to h'0 when incremented at delay value h'3ff. Wraps around to h`3ff when decremented at delay value h`0. |
0x0E | ODLY3 | Bitslice-3 odelay: Controls one tap increments/decrements or coarse increments/decrements based on CntvalueIn. Wraps around to h'0 when incremented at delay value h'3ff. Wraps around to h`3ff when decremented at delay value h`0. |
0x0F | ODLY4 | Bitslice-4 odelay: Controls one tap increments/decrements or coarse increments/decrements based on CntvalueIn. Wraps around to h'0 when incremented at delay value h'3ff. Wraps around to h`3ff when decremented at delay value h`0. |
0x10 | ODLY5 | Bitslice-5 odelay: Controls one tap increments/decrements or coarse increments/decrements based on CntvalueIn. Wraps around to h'0 when incremented at delay value h'3ff. Wraps around to h`3ff when decremented at delay value h`0. |
0x11 | BS_RST_MASK | Bitslice reset mask: When set, the corresponding
bitslice will not get reset when a 1 is written to
BS_RESET_CTRL.bs_reset. Bitslice-tri reset mask: When set, the tristate bitslice will not get reset when a 1 is written to BS_RESET_CTRL.bs_reset_tri. Monitor reset mask: When set, monitor logic will not get reset when a 1 is written to BS_RESET_CTRL.mon_reset. |
0x12 | IDLY0 | Bitslice-0 idelay: Controls one tap increments/decrements or coarse increments/decrements based on CntvalueIn. Wraps around to h'0 when incremented at delay value h'3ff. Wraps around to h`3ff when decremented at delay value h`0. |
0x13 | IDLY1 | Bitslice-1 idelay: Controls one tap increments/decrements or coarse increments/decrements based on CntvalueIn. Wraps around to h'0 when incremented at delay value h'3ff. Wraps around to h`3ff when decremented at delay value h`0. |
0x14 | IDLY2 | Bitslice-2 idelay: Controls one tap increments/decrements or coarse increments/decrements based on CntvalueIn. Wraps around to h'0 when incremented at delay value h'3ff. Wraps around to h`3ff when decremented at delay value h`0. |
0x15 | IDLY3 | Bitslice-3 idelay: Controls one tap increments/decrements or coarse increments/decrements based on CntvalueIn. Wraps around to h'0 when incremented at delay value h'3ff. Wraps around to h`3ff when decremented at delay value h`0. |
0x16 | IDLY4 | Bitslice-4 idelay: Controls one tap increments/decrements or coarse increments/decrements based on CntvalueIn. Wraps around to h'0 when incremented at delay value h'3ff. Wraps around to h`3ff when decremented at delay value h`0. |
0x17 | IDLY5 | Bitslice-5 idelay: Controls one tap increments/decrements or coarse increments/decrements based on CntvalueIn. Wraps around to h'0 when incremented at delay value h'3ff. Wraps around to h`3ff when decremented at delay value h`0. |
0x18 | CRSE_DLY | Coarse Delay (32 tap CRSE DELAY to provide 1.8 ns delay in front of PQTR and NQTR for slow interfaces): Controls one tap increments/decrements or loading coarse delay value. |
0x19 | PQTR_ALIGN | PQTR align delay value |
0x1A | NQTR_ALIGN | NQTR align delay value |
0x1B | MON_ALIGN | Monitor align delay value |
0x1C | IDLY0_ALIGN | IDELAY0 align delay value |
0x1D | IDLY1_ALIGN | IDELAY1 align delay value |
0x1E | IDLY2_ALIGN | IDELAY2 align delay value |
0x1F | IDLY3_ALIGN | IDELAY3 align delay value |
0x20 | IDLY4_ALIGN | IDELAY4 align delay value |
0x21 | IDLY5_ALIGN | IDELAY5 align delay value |
0x22 | RLDLYUPDATE | RlDlyRank Update: Controls rank read level delay increments/decrements by one tap or coarse steps. Increments/decrements by one tap or coarse steps if corresponding rank mask bit not set. |
0x2B | WL_TRAIN | Write level mode: When set, XPHY is put in write leveling mode
otherwise normal operation. Delay control enable VTC: When set, XPHY prepares the base line for the VT compensation and upon completion it assert PHY_RDY. Enable transmit clockgen 1tck gap: When set, transmit clockgen suppress the last ddr_strb for the current burst and first strobe of the next burst when it detects the 1tck gap between two write bursts so that tristate is inactive between the bursts. BISC Pause: When set, BISC state machine pauses. |
0x2C | WLDLYRNK0 | Rank-0 write level fine and coarse delay |
0x2D | WLDLYRNK1 | Rank-1 write level fine and coarse delay |
0x2E | WLDLYRNK2 | Rank-2 write level fine and coarse delay |
0x2F | WLDLYRNK3 | Rank-3 write level fine and coarse delay |
0x30 | RLDLYRNK0 | Rank-0 read level fine and coarse delay and updates read delay rank registers. |
0x31 | RLDLYRNK1 | Rank-1 read level fine and coarse delay and updates read delay rank registers. |
0x32 | RLDLYRNK2 | Rank-2 read level fine and coarse delay and updates read delay rank registers. |
0x33 | RLDLYRNK3 | Rank-3 read level fine and coarse delay and updates read delay rank registers. |
0x3B | INCDEC_CRSE | Increment/decrement coarse adjustment value |
0x3E | NIBBLE_CTRL2 | Nibble Control 2: Per bitslice ODT control. When set, ODT is disabled
otherwise it is enabled. Controls start of DQS gate training, enables DQS gate VT tracking, controls per rank versus single rank gate delay tracking, controls if BISC employs coarse delay for quarter delay push out for PDQS and NDQS if PQTR and NQTR saturate and controls preamble for DDR4. |
0x41 | VREF_CTRL | 10-bit VREF Setting Provides selection of VREF control from Fabric versus IOB config register. |
0x49 | CRSE_ADJUST | Coarse adjust value. Default value is programmed to CRSE_ADJUST attribute. |
0x4B | DIS_DYN_MODE | Disable TX bitslice Dynamic mode |