The table shows the PHY control signals for a PHY only option.
| Signal | I/O | Description |
|---|---|---|
| calDone | O | Indication that the DRAM is powered up, initialized, and calibration is complete. This indicates that the PHY interface is available to send commands to the DRAM. Active-High. |
| mcRdCAS | I | Read CAS command issued. This signal must be asserted for one system clock if and only if a read CAS command is asserted on one of the command slots at the PHY command/address input ports. Hold at 0x0 until calDone asserts. Active-High. |
| mcWrCAS | I | Write CAS command issued. This signal must be asserted for one system clock if and only if a write CAS command is asserted on one of the command slots at the PHY command/address input ports. Hold at 0x0 until calDone asserts. Active-High. |
| winRank[1:0] | I | Target rank for CAS commands. This value indicates which rank a CAS command is issued to. It must be valid when either mcRdCAS or mcWrCAS is asserted. The PHY passes the value from this input to the XPHY to select the calibration results for the target rank of a CAS command in multi-rank systems. In a single-rank system, this input port can be tied to 0x0. |
| mcCasSlot[1:0] | I | CAS command slot select. The PHY only supports CAS commands on even
command slots. mcCasSlot indicates which of these two possible command
slots a read CAS or write CAS was issued on. mcCasSlot is used by the
PHY to generate XPHY control signals, like DQ output enables, that need
DRAM clock cycle resolution relative to the command slot used for a CAS
command. Valid values after calDone asserts are 0x0 and 0x2. Hold at 0x0 until calDone asserts. This signal must be valid if mcRdCAS or mcWrCAS is asserted. For more information, see the CAS Command Timing Limitations section. |
| mcCasSlot2 | I | CAS slot 2 select. mcCasSlot2 serves a similar purpose as the
mcCasSlot[1:0] signal, but mcCasSlot2 is used in timing critical logic
in the PHY. Ideally mcCasSlot2 should be driven from separate flops from
mcCasSlot[1:0] to allow synthesis/implementation to better optimize
timing. mcCasSlot2 and mcCasSlot[1:0] must always be consistent if
mcRdCAS or mcWrCAS is asserted. To be consistent, the following must be TRUE: mcCasSlot2==mcCasSlot[1]. Hold at 0x0 until calDone asserts. Active-High. |
| winInjTxn | I | Optional read command type indication. When winInjTxn is asserted
High on the same cycle as mcRdCAS, the read does not generate an
assertion on rdDataEn when it completes. Instead, the per_rd_done signal
asserts, indicating that a special type of read has completed and that
its data is valid on the rdData output. In DDR4 SDRAM controller designs, the winInjTxn/per_rd_done signals are used to track non-system read traffic by asserting winInjTxn only on read commands issued for the purpose of VT tracking. |
| winRmw | I | Optional read command type indication. When winRmw is asserted High
on the same cycle as mcRdCAS, the read does not generate an assertion on
rdDataEn when it completes. Instead, the rmw_rd_done signal asserts,
indicating that a special type of read has completed and that its data
is valid on the rdData output. In DDR4 SDRAM controller designs, the winRmw/rmw_rd_done signals are used to track reads issued as part of a read-modify-write flow. The DDR4 SDRAM controller asserts winRmw only on read commands that are issued for the read phase of a RMW sequence. |
| winBuf[DATA_BUF_ADDR_WIDTH- 1:0] | I | Optional control signal. When either mcRdCAS or mcWrCAS is asserted,
PHY stores the value on the winBuf signal. The value is returned on
rdDataAddr or wrDataAddr, depending on whether mcRdCAS or mcWrCAS was
used to capture winBuf. In DDR4 SDRAM controller designs, these signals are used to track the data buffer address used to source write data or sink read return data. |
| gt_data_ready | I | Update VT Tracking. This signal triggers the PHY to read RIU registers in the XPHY that measure how well the DQS Gate signal is aligned to the center of the read DQS preamble, and then adjust the alignment if needed. This signal must be asserted periodically to keep the DQS Gate aligned as voltage and temperature drift. For more information, see the VT Tracking section. Hold at 0x0 until calDone asserts. Active-High. |
The following figure shows a write command example. On cycle N, write command
“A” is asserted on the PHY command/address inputs in the slot0 position. The mcWrCAS input is also asserted on cycle N, and a valid rank
value is asserted on the winRank signal. In the
following figure, there is only one CS_n pin, so the
only valid winRank value is 0x0. The mcCasSlot[1:0] and mcCasSlot2 signals are valid on cycle N, and specify
slot0.
Write command “B” is then asserted on cycle N + 1 in the slot2 position, with
mcWrCAS, winRank,
mcCasSlot[1:0], and mcCasSlot2 asserted to valid
values as well. On cycle M, PHY asserts wrDataEn to indicate that
wrData and wrDataMask values corresponding to
command A need to be driven on cycle M + 1.
The following figure shows the data and mask widths assuming an 8-bit DDR4 DQ bus width. The delay between cycle N and
cycle M is controlled by the PHY, based on the CWL and AL settings of the DRAM. wrDataEn also asserts on cycle M + 1 to indicate that
wrData and wrDataMask values for command B are required on cycle M + 2. Although this
example shows that wrDataEn is asserted on two
consecutive system clock cycles, you should not assume this will always be the case,
even if mcWrCAS is asserted on consecutive clock
cycles as is shown here. There is no data buffering in the PHY and data is pulled into
the PHY just in time. Depending on the CWL/AL settings and the command slot used,
consecutive mcWrCAS assertions might not result in
consecutive wrDataEn assertions.
The following figure shows a read command example. Read commands are issued on
cycles N and N + 1 in slot positions 0 and 2, respectively. The
mcRdCAS, winRank, mcCasSlot, and
mcCasSlot2 are asserted on these cycles as well. On cycles M + 1
and M + 2, PHY asserts rdDataEn and rdData.
